The present disclosure relates to operating different processor cache levels of a cache hierarchy, in particular a cache hierarchy intended for use with a processor with pipelined execution. In this concern, saving hardware for tracking level 1 cache misses may be considered.
A cache is a circuitry combined with switching logic that arranged to keep a processor's access time to fetch data from memory, be it data or instruction data, as short as possible. This is required because, in recent years, processor velocity has grown considerably faster than the velocity of accessing memory. Thus, data that has already been fetched from main memory is intermediately stored in a buffer called cache, the cache being arranged very close to the processor and being a very fast though small piece of memory. During further development of increasing processor velocities without correspondingly increasing the velocity of the main memory, further buffer levels were necessary.
Nowadays, several cache levels are spread over a computer system, a level 1 cache being arranged most closely on the processor die. Usually, a processor may comprise a level 1 data cache, a level 1 instruction cache, and a level 2 cache. A level 3 cache and main memory may be distributed over the computer system.
When the processor requires data, be it data as such or instruction data, the processor issues a request for the data. Cache logic arranged on the chip tries first to find the requested in a corresponding level 1 cache, or, L1 cache. This is done via the help of a directory associated with the L1 cache together with, e.g., the information as to whether a referenced data is valid or not.
In the case, the data could not be found or is invalid, a miss event has occurred, meaning that the requested data was missed in the L1 cache. In that case, counters for tracking statistical data may be incremented or decremented, respectively, e.g., a hit counter or a miss counter. Further, a fetch address register, that might be abbreviated in circumstances as FAR, might be filled up with the requested address or parts of it. It is also considered to use another appropriate register. However, for a better comprehensibility, in the following, it will mostly be referred to the fetch address register. Based on this entry, a request to a level 2 cache, L2 cache, may be sent, followed by a similar logic. For example, when an L2 miss event occurs, it will be necessary to issue a further request, now directed to the next higher cache level, i.e., here, the L3 cache. This may repeat, up a cache hierarchy, until the main memory is reached. In this hierarchy, trying to retrieve the necessary data from the main memory, is the ultima ratio.
In the case of a deep pipeline, the feedback as to whether or not the request to the L2 cache as resulted into a hit or a miss, may consume considerable time.